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Altera_Forum
Honored Contributor
Honored ContributorVHDL integer causing RTL and Gate level simulation difference
I have a general question regarding the use of integers in VHDL. If I have a lot of Array defined, we have to use integer as its index when accessing the arrays. However, when the index is conv...
Altera_ForumHonored Contributor
Honored ContributorThe problem is brought up with uninialized std_logic and derived types, that have a default value of 'U' in functional simulation and '0' in real hardware. Add '0' initializers to the definition of register signals or add an explicite reset initialization to achieve consistent simulation.
