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Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks.
External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be generated using 100MHz clock startin g from rising edge of 124Hz clock.22 Replies
Altera_Forum--- Quote Start --- whats wrong with clock enables? --- Quote End --- clock enable is not working in this case since the 10MHz is to be synchronized with two un-synchronized clocks 100MHz and 124Hz- Altera_Forum
whats wrong with clock enables?
