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Honored Contributor
Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- whats wrong with clock enables? --- Quote End --- clock enable is not working in this case since the 10MHz is to be synchronized with two un-synchronized clocks 100MHz and 124Hz
