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Altera_Forum
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13 years ago

VHDL Help

Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks.

External clocks are: 100Mhz and 124 Hz

Clock to be generated: 10MHz

The 10MHz clock is to be generated using 100MHz clock startin g from rising edge of 124Hz clock.

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  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    but 124Hz clock is already there from an external source...i think i didn't get you

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes. But the code you have just samples the 10Mhz clock, it doesnt synchronise it. So the output clock will not be 10MHz, it will be, at most, 62Hz.