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Honored Contributor
Honored ContributorVHDL Help
Please help me to generate a clock in VHDL synchronised with rising edges of two external clocks. External clocks are: 100Mhz and 124 Hz Clock to be generated: 10MHz The 10MHz clock is to be g...
Altera_ForumHonored Contributor
Honored ContributorYes. But the code you have just samples the 10Mhz clock, it doesnt synchronise it. So the output clock will not be 10MHz, it will be, at most, 62Hz.
