Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThe biggest problem is that you are treating VHDL like a programming language. VHDL stands for VHSIC (very high speed integrated circuit) Hardware description Language. You use the language to describe hardware. Unless you get this fundamental understood, any behavioural VHDL is going to fall to peices when you try and synthesise it.
So the best thing for you to do might be start over. First think about/draw out the logic circuit that you're trying to achieve. When you know what gates/registers you need, then write it up in VHDL. Clocks are an essential part of FPGA logic, but not derived clocks - system clocks. You can then use something like baud_tick as a register enable. This way the registers are always clocked with the same stable low skew clock, but the enable only lets data through at the correct time. Back to you not understanding my sentence: Procedures are almost like mini entities. Entries in a procedure can be 3 types: constant, variable or signal. Each entry can be of mode in, out or inout (like a entity). In signals default to constant, out or inout default to variable. So look at the following code:
procedure do_something( a : in integer; --This is a constant.
variable b : out integer;
c : inout integer;; --defaults to variable
signal d : inout integer;
signal e : out integer
) is
begin
b := a + 10;
c := c + a;
d <= c + a; --as c is a variable, d = c + a + a.
e <= d + a; --as d is a signal, e uses old value of d before the update above.
end procedure;
------------------------
--Call the procedure
------------------------
do_something( a => some_signal, --reads the value of "some_signal" when the procedure is called, internally treated as a constant
b => op_var, --op_var cannot be read inside the procedure, only written
c => some_var, --procedure can read "some_var" and write back to it
d => output --like b above, but with a signal
);
Generally, procedures are a good way of tidying up repeated code that assigns the same signals over and over again. Functions are great for tidying away complex assignemnets to a single signal/variable/constant.