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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL Counter

I am new to VHDL, and I am trying to create a counter that will count up from 0 to X when a signal called enable will be true. I get errors like Latches are generated for incomplete case or if ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Proof of what I am saying, this code: 


  if(enable='1') then
      r_reg <= r_reg + 1;
  else
      r_reg <=(others => '0');
  end if;
Will only get executed at posedge clk NO MATTER what.

And that means: adding "enable" to the sensitivity list will only confuse your code (for both humans and compilers).

Besides that, when enable changes, surely there will be a clk posedge shortly after that (after all clk is a PERIODIC signal), and at that point your code WILL get evaluated (have no fear).

Besides that I also know ISE tools and I know what I'm saying here :)