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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL Counter

I am new to VHDL, and I am trying to create a counter that will count up from 0 to X when a signal called enable will be true. I get errors like Latches are generated for incomplete case or if ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes...I have connected everything. i think the way i am going to approach this problem will be the dumb way. I will let the counter run and use a d-ff to latch only the last value so the fifo only gets the largest count.

I don't know how to make counter that resets itself on an enable trigger and only provides the last count... thanks for your help though