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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL Counter

I am new to VHDL, and I am trying to create a counter that will count up from 0 to X when a signal called enable will be true. I get errors like Latches are generated for incomplete case or if ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Tricky, as usual, thank you for helping wash off all the newb on my shirt.