VHDL Counter

Hola Homie,

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
----------------------------------->
Entity YourCount is
  Generic( n: integer := 16);
  Port(
        clk : in std_logic ;
        rst : in std_logic;
        enable : in std_logic;
        max_ticks : out std_logic;
        Cnts_out : out Unsigned (N-1 downto 0)
        );
End YourCount;
----------------------------------------->
Architecture Count of YourCount is
Begin
  
  ------------- CountBe quick ---------------------------
  CountBeQuick : Process(clk,rst,enable)
    Variable count : integer range 0 to ((2**N)-1);                -- integer range 0 to 65,535
  Begin
    if(rst = '1') then
      count := 0;            -- clear count
      max_ticks <= '0';     -- clear max ticks
    elsif (clk'EVENT and clk ='1' and enable = '1') then
      count := count + 1; 
      if (count = ((2**N)-1)) then
        max_ticks <= '1';     -- max_ticks stays high till reset
       end if;
    end if;
    
    if (enable'Event and enable ='0') then     -- this transfers count value and clears count
      Cnts_out <= TO_UNSIGNED(count,N);  -- converts count to unsigned of length N
      count := 0;
    end if;
   End Process CountBeQuick;
   ----------------------------------------------------------
End Count;