[VHDL] Compilation Order

--- Quote Start ---

The VHDL compiler needs an order, as packages will need to be compiled before entities etc. And if you use direct instantiation, you need the entity you are instantiating compiled before you instantiate it, otherwise the compiler throws an error.

You may be getting confused between compilation and mapping. If you use component declarations, then you are pretty much free to compile the files in whatever order you want and it is the mapping stage (after compilation/elaboration) that will map entities on to components.

I dont like using components because you have to essentially maintain the same code twice or more (once for the entity, once for the component). You also have to wait until elaboration finishes to find a mapping error. With direct instantiation it is the compiler that does the work, so it is much quicker to find errors, but compile order becomes important.

--- Quote End ---

I still beg to differ: I just re-arranged an old project into using a mix of entity.work and component declarations.

This is the output of the analysis and synthesis step:

Info (12021): Found 2 design units, including 0 entities, in source file ops2/ops2_types.vhd
Info (12021): Found 2 design units, including 1 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/combmuxs/combmuxs.vhd
Info (12021): Found 2 design units, including 1 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/combmux/combmux.vhd
Info (12021): Found 2 design units, including 1 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/regmux/regmux.vhd
Info (12021): Found 2 design units, including 1 entities, in source file reg2/reg2.vhd
Info (12021): Found 2 design units, including 0 entities, in source file /qdesigns/bv5fpga/c-cam/bb/vhdl_packages/cc_data_types.vhd
Info (12021): Found 2 design units, including 1 entities, in source file id2/id2.vhd
Info (12021): Found 2 design units, including 1 entities, in source file pc2/pc2.vhd
Info (12021): Found 8 design units, including 4 entities, in source file /qdesigns/bv5fpga/c-cam/bb/gates/wide_logic/wide_logic.vhd
Info (12021): Found 2 design units, including 1 entities, in source file alu2/alu2.vhd
Info (12021): Found 2 design units, including 1 entities, in source file reg2/indexreg/indexreg.vhd
Info (12021): Found 2 design units, including 1 entities, in source file ops2/ops2.vhd
Info (12127): Elaborating entity "ops2" for the top level hierarchy
Info (12128): Elaborating entity "id2" for hierarchy "id2:ids"
Info (12128): Elaborating entity "combmux" for hierarchy "id2:ids|combmux:aludmux"
Info (12128): Elaborating entity "pc2" for hierarchy "pc2:p"
Info (12128): Elaborating entity "altsyncram" for hierarchy "pc2:p|altsyncram:instructionmemory"
Info (12130): Elaborated megafunction instantiation "pc2:p|altsyncram:instructionmemory"
Info (12133): Instantiated megafunction "pc2:p|altsyncram:instructionmemory" with the following parameter:
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_5rq3.tdf
Info (12128): Elaborating entity "altsyncram_5rq3" for hierarchy "pc2:p|altsyncram:instructionmemory|altsyncram_5rq3:auto_generated"
Info (12128): Elaborating entity "reg2" for hierarchy "reg2:regio"
Info (12128): Elaborating entity "indexreg" for hierarchy "reg2:regio|indexreg:x"
Info (12128): Elaborating entity "altsyncram" for hierarchy "reg2:regio|altsyncram:regmemory"
Info (12130): Elaborated megafunction instantiation "reg2:regio|altsyncram:regmemory"
Info (12133): Instantiated megafunction "reg2:regio|altsyncram:regmemory" with the following parameter:
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ouq3.tdf
Info (12128): Elaborating entity "altsyncram_ouq3" for hierarchy "reg2:regio|altsyncram:regmemory|altsyncram_ouq3:auto_generated"
Info (12128): Elaborating entity "alu2" for hierarchy "alu2:a"
Info (12128): Elaborating entity "LPM_ADD_SUB" for hierarchy "alu2:a|LPM_ADD_SUB:addsub"
Info (12130): Elaborated megafunction instantiation "alu2:a|LPM_ADD_SUB:addsub"
Info (12133): Instantiated megafunction "alu2:a|LPM_ADD_SUB:addsub" with the following parameter:
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_d8h.tdf
Info (12128): Elaborating entity "add_sub_d8h" for hierarchy "alu2:a|LPM_ADD_SUB:addsub|add_sub_d8h:auto_generated"
Info (12128): Elaborating entity "wide_and" for hierarchy "alu2:a|wide_and:wand"
Info (12128): Elaborating entity "wide_or" for hierarchy "alu2:a|wide_or:wor"
Info (12128): Elaborating entity "wide_xor" for hierarchy "alu2:a|wide_xor:wxor"
Info (12128): Elaborating entity "combmux" for hierarchy "alu2:a|combmux:logresultmux"
Info (12128): Elaborating entity "regmux" for hierarchy "regmux:iomux"
Info (12128): Elaborating entity "combmux" for hierarchy "combmux:imux"

The first 12 lines represent the order in the Assignments->Settings->Files.

And the following lines show the order of elaboration ...