[VHDL] Compilation Order

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I don't think this is completely right: The compiler will start with the top-level VHDL and infer from there on; it only needs to know where the childeren are. IMO the only order to observe is the one of the .sdc files, in the case of one of the .sdc needing info of a higher level one.

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The VHDL compiler needs an order, as packages will need to be compiled before entities etc. And if you use direct instantiation, you need the entity you are instantiating compiled before you instantiate it, otherwise the compiler throws an error.

You may be getting confused between compilation and mapping. If you use component declarations, then you are pretty much free to compile the files in whatever order you want and it is the mapping stage (after compilation/elaboration) that will map entities on to components.

I dont like using components because you have to essentially maintain the same code twice or more (once for the entity, once for the component). You also have to wait until elaboration finishes to find a mapping error. With direct instantiation it is the compiler that does the work, so it is much quicker to find errors, but compile order becomes important.