Forum Discussion
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- it will compile them in the order they appear in the .qsf file. You can change the order in assignments -> settings -> files Or add a group of files via a .qip file (a .qip file is really just a tcl file) --- Quote End --- I don't think this is completely right: The compiler will start with the top-level VHDL and infer from there on; it only needs to know where the childeren are. IMO the only order to observe is the one of the .sdc files, in the case of one of the .sdc needing info of a higher level one.