Vhdl codes for 8-bit ring counter

Hi,

I have VHDL codes for an 8-bit ring counter but when i try to compile it there are always errors (8 errors). I even tried editing some lines (lines 2 and 3) and compiled again and the errors reduced to 4 but the surprising thing is the corrections i made altered the conventional mode of entering the code. Although the errors were reduced to 4, I don't quite understand why that was possible.Please find below the first code and the edited code. I would really appreciate help on this.

first code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ring_counter is

port (

DAT_O : out unsigned(7 downto 0);

RST_I : in std_logic;

CLK_I : in std_logic

);

end ring_counter;

architecture Behavioral of ring_counter is

signal temp : unsigned(7 downto 0):=(others => '0');

begin

DAT_O <= temp;

process(CLK_I)

begin

if( rising_edge(CLK_I) ) then

if (RST_I = '1') then

temp <= (0=> '1', others => '0');

else

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(4) <= temp(3);

temp(5) <= temp(4);

temp(6) <= temp(5);

temp(7) <= temp(6);

temp(0) <= temp(7);

end if;

end if;

end process;

end Behavioral;

edited code

library IEEE;

use IEEE.ALL;

use IEEE.ALL;

entity ring_counter is

port (

DAT_O : out unsigned(7 downto 0);

RST_I : in std_logic;

CLK_I : in std_logic

);

end ring_counter;

architecture Behavioral of ring_counter is

signal temp : unsigned(7 downto 0):=(others => '0');

begin

DAT_O <= temp;

process(CLK_I)

begin

if( rising_edge(CLK_I) ) then

if (RST_I = '1') then

temp <= (0=> '1', others => '0');

else

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(4) <= temp(3);

temp(5) <= temp(4);

temp(6) <= temp(5);

temp(7) <= temp(6);

temp(0) <= temp(7);

end if;

end if;

end process;

end Behavioral;