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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL can simulate but not implement?

Hello, I'm trying to write a program that basically has 3 inputs and 1 output. One input, CNVST will receive a short 2 us pulse every so often. Once that 2 us pulse is received the output RD needs to drop low on the next falling edge of input 2, CLK. RD then needs to stay low until RST=1. I've attached the code that I wrote, and it works in simulation but when I try to implement the design I get this error: "Bad Condition in wait statement, or only one clock per process"

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for the tips. After a bit of brainstorming I was able to get the desired output using a custom block, d flip flop, 16 bit counter, and a few inverters.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Your code is perfectly legal, but the synthesis tools (who will translate your VHDL into netlists) cannot cope with it. In general, wait statements are tough for synthesis tools. A few accept "wait for rising_edge(clk);", the others don't accept any wait statements.

    The basic skeleton the synthesizer likes is this: 

    	process (clk, rst) is
	begin
		if rst = '0' then  -- '0' for active-low reset or '1' for active-high reset
			-- reset your signals
		elsif rising_edge(clk) then
			-- do stuff
		end if;
	end proces;

    If I try to fiddle your code into this skeleton, I get something like this: 

    ARCHITECTURE RTL OF ENABLE IS
BEGIN
	PROCESS(clk)
	BEGIN
		if rst = '1' then
			RD <= '1';
		elsif(rising_edge(clk)) then
			IF CNVST = '1' THEN
				RD <= '0';
			end if;
		END IF;
	END PROCESS;
END;

    No need to draw a diagram first. This will limit your hardware designs to things you can visualize. If you just stick to the skeleton above, you can write complex state machines that you could never draw if you force yourself to think of flip-flops and gates.

    In order to get a feeling of how the synthesis tool works, it is useful to inspect the synthesis results.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    what you have writen is perfectly legal VHDL, but has no relation to any real hardware, which is what is causing the problem. The code you have written shows you are thinking like a software programmer. VHDL is a description language, not a programming language.

    I suggest you draw your circuit out on a peice of paper before trying to describe it in VHDL.