vhdl -division program

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but 1/b also has a division then how can it accept?. or how to do it

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you can look at 'a' as an 8 bit integer, say 51 which is 00110011

say you wanted to divide by 3. we will actually multiply by 1/3 in 8 bits fractional, so 'b' is 0.010101

00110011 x 0.010101 = 000010001.0000100

51 * 0.328125 = 17.03125

the decimal point is an abstraction. anyhow, this may work for your application (maybe if 'b' only has a few possible values) and only uses a 9 bit signed multiplier. hopefully someone can double check my work, its been awhile...

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Sounds like poor mans pipelining, but an interesting suggestion though.

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if by poor you mean lazy, certainly. :)

it would be nice if register retiming could meet the fmax of an lpm function. i haven't found it to do so with wide multipliers (24 bit) in CIII either.

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but 1/b also has a division then how can it accept?. or how to do it

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Hence why I said take it off FPGA onto something like a processor.

Division can be done fine on an FPGA, it just eats through resources.

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Or the best solution is to redesign the algorithm so that you dont have to do the divide in the first place - stick to multiplies instead.

a/b = a * 1/b. Do the 1/b function on something else (like a processor) if you can.

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but 1/b also has a division then how can it accept?. or how to do it

Or the best solution is to redesign the algorithm so that you dont have to do the divide in the first place - stick to multiplies instead.

a/b = a * 1/b. Do the 1/b function on something else (like a processor) if you can.

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It does, under the conditions I told. (Valid at least for V9.0 and later).

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If i use version 9 or later will it accept the division . i have not yet used version 9.

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you can try adding some extra registers and turning on register retiming

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Sounds like poor mans pipelining, but an interesting suggestion though. Seriously, if the infered divider doesn't achieve the intended speed, you should use an explicite instantiation.