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Altera_Forum
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16 years ago

VHDL - CASE related question

Hello, This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROC...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thank you very mcuh Tricky, mmTsuchi.

Looks like a have long way to go.

One thing that I can't understand is,

A GENERATE block and a PROCESS block, 'how many' instructions can a FPGA perform? It ofcourse depends on the model, but as a programmer, how would you know that a block of code can be executed within a clock cycle? Or is it not like that? Is possible for a block of PROCESS to take several clock cycles to execute completely?

Thank you.