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I recommend to use only std_(u)logic, std_(u)ogic_vector(... downto ...) for ports of an entity.
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Personally, Id recommend having ports on entities of the type that best reflects what it is. Its so annoying have to do type conversions all the time when 2 connected entites are using integers and signed/unsigned types internally. At the top level you will need to use std_logic(_vector) or signed/unsigned though because you have to constrain individual bits to single pins. But internally, use whatever best reflects what the signal actually is.
Types Ive used fine for ports on entities (not top level)
Std_(u)logic(_vector)
signed
unsigned
boolean
integer/natural/positve (remember to constrain them else you'll have lots of spare bits)
sfixed/ufixed
records containing any of the above
arrays of any of the above
Records come into play when you're trying to encapsulate stuff, especially registers.
also, ennumerated types should be fine as port connections.
In addition, memories can be infered from most of the above.
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