VHDL - CASE related question

Completely agree with Tricky.

Altera gives on website guidelines and coding style like http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=vhdl%20guidelines

--- Quote Start ---

LIBRARY ieee;

USE ieee.STD_LOGIC_1164.all;

--- Quote End ---

I recommend to use only std_(u)logic, std_(u)ogic_vector(... downto ...) for ports of an entity.

Be aware of what is synthesizable or not (like "after 25 ns", file operations...)

...

think about circuit and describe it in vhdl.