Very simple question, first time using Verilog here...

Harald is right, you should do something like

`timescale 100 ns / 10 ns

module obj_7bit_paritybitgenerator ( bus_bits, parityresult );

//Define the inputs/outputs for the circuit.

input [6:0] bus_bits;

output [7:0] parityresult;

wire [7:0] parityresult;

// maybe your parity bit must be inverted.

assign parityresult[7] = bus_bits[0] ^ bus_bits[1] ^ bus_bits[2] ^ bus_bits[3] ^ bus_bits[4] ^ bus_bits[5] ^ bus_bits[6];

// question what about the parityresult[6:0] ???

endmodule

But be aware that your parity is a wire and therefore could have some glitches.

the next module should synchronize it to a clock.

so always use full synchronous design whenever possible

// always @ ( posedge clk )

// begin

// insert your code here ...

// end

regards

michael