Verilog Synthesis Q

FvM,

Just saw your last post. My apologies for the code snippets. I wasn't trying to be evasive. I didn't want to post a plethora of code and ask you to fix it. I wanted to work through the issue so I understood why? Both your and rbug's guidance has been very helpful.

I was planning on asking about inferred RAM upon completion of my project as I din't quite understand the implications. Based on today's thread and your guidance, I understand now.....

You help is truly appreciated....

Have a great day.

Mark