Verilog Synthesis Q

DING..I think the light just went on. I have a different module that does a similar thing. However, it doesn't have to go through an complex logic. It simply sets a bit in a similar array based on the address that comes in. It works fine. It is also accessed via the NIOS application as well as from my custom code. However, all of the accesses (from both the NIOs and my FPGA code) are in the same synchronous always construct. The synthesizer displays a message that it is inferring RAM and now I think I understand why. Since both types of accesses are in the same always construct the synthesizer configures that array as RAM. However, in my decision array instance I was attempting to access the array via two different always constructs. In one instance as a Avalon MM slave and in the second as a direct write. In the second case, since i don't conform to the memory interface stndards, the synthesizer can't resolve it as memory and thus tries to make it registers.

Am I close?

Anyway, as soon as I moved the write access into the same always construct, everything started to compile.

I'll see how this progresses today. Hopefully, you won't hear from me any mre.

THANKS AGAIN TO BOTH OF YOU FOR YOUR HELP. I TRULY APPRECIATE YOU MENTORSHIP.