Verilog Synthesis Q

First question: Yeah! I got one right.....8>)

Second question: Yes, I am referencing the code which writes to the array in# 6. I am reading it via a NIOS CPU application via an Avaon MM slave interface. I'm guessing that even though I remove the write statement in# 6, because the array is accessed from the NIOS, it is being instantiated as RAM. The NIOS interface works perfectly (Can read and write to the array). As soon as I add something as simple as:

decision[0] <= 1;

to the code from# 6, i get the ram inference issue.

At this point I'm working through the I don't know what I don't know issue. I appreciate your continued guidance...

ME