Verilog Synthesis Q

Ok, that answers my questions.

No, the Avalon-MM slave doesn't force anything. It's the reverse, actually.

The way you've coded the read/write access from the Avalon-MM interface allows Quartus to infer RAM blocks. Which is happily does.

When you add the extra code to write the array, you're adding something that is preventing Quartus from inferring a RAM.

There are two reasons for Quartus not being able to infer a RAM.

1. It's not possible. Your code describes a behaviour that the M9K blocks can't implement: asynchronous access or clearing the contents for example. Quartus tends to provide messages in those cases.

2. Software limitation. Synthesis is somewhat pattern orientated and Quartus doesn't always recognize the code. That's why we have to follow the templates.