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Altera_Forum
Honored Contributor
Honored ContributorVerilog Synthesis Q
Am bumping into a synthesis problem inside of an always construct. Simplified code is reg true_or_false[0:9999]; reg a; always (negedge clk) begin if (a <5000) true_or_false...
Altera_ForumHonored Contributor
Honored ContributorFirst question:
Indeed, the write condition is not required for the code to be inferred into RAM. You'll just get a RAM block which is constantly writing into the position indicated by address. Second question: I assume you refer to the code in your post# 6. Two questions there. 1. If you don't have a statement which writes the RAM, the reads always return 0 and thus Quartus should optimize it away entirely. 2. How do you read it?
