Verilog Synthesis Q

Another thought as I work my way through this....

The array in question is also accessed from the NIOS CPU via an Avalon MM Slave interface. This works quite well. My NIOS application successfully reads and writes to the same array I am trying to access. I do have a single bit entity that defines whether the NIOS or my custom FPGA code has access to the array. Does the use of the Avalon MM slave "force" quartus to define the array as memory (thus why it shows up as memory bits in the compilation report)?

Thanks again,

ME