Verilog Synthesis Q

Thank to both of you. I'm starting to get there. Please bear with a couple more dumb questions.

Have been reading the HDL coding guidelines and I'm sure they will make sense once I solve the problem. One question. In your example, you specify a write signal. My understanding is that I don't need the write signal to access the array. Rather, since the always loop conforms to the standards you discuss, the synthesizer defines the array as ram rather than registers.

A second question. In my example, if I remove the statement that actully attempts to write to the array, it synthesizes and appears to place the array in RAM.

Thank you both for your continued patience as I learn....

ME