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Altera_Forum
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14 years ago

Verilog Synthesis Q

Am bumping into a synthesis problem inside of an always construct. Simplified code is reg true_or_false[0:9999]; reg a; always (negedge clk) begin if (a <5000) true_or_false...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

What FvM means is that you need to write your code while meeting Quartus templates for inferring RAM for your FPGA.

They are documented in the HDL coding guidelines handbook, but it's something like this 


// 1x128k memory
reg memory; 
always @ (posedge clk) begin
if (write) 
    memory <= data_in;
data_out <= memory;
end

If your Verilog code describes something Quartus doesn't know or cannot map to RAM (M9K) blocks, Quartus will try to map it to registers.

Since the FPGA in question only has ~115k registers, they're not enough to implement your 128 kbit table, plus all the remaining logic.