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Altera_Forum
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14 years ago

Verilog Synthesis Q

Am bumping into a synthesis problem inside of an always construct. Simplified code is reg true_or_false[0:9999]; reg a; always (negedge clk) begin if (a <5000) true_or_false...
Altera_Forum's avatar
Altera_Forum
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14 years ago

btw, it's in a synchronous always which contains a state machine...

thanks agagin