Verilog Synthesis Q

SO I tried something a little different. Rather than creating the if else construct, I did something like this (inside a state machine):

branch_found:

begin

greater_than_false_address[0] <= (current_tdr_address >= branch_false_address[0]) ? 1 :0;

less_than_true_address[0] <= (current_tdr_address < branch_true_address[0]) ? 1 : 0;

equal_to_true_address[0] <= (current_tdr_address == branch_true_address[0]) ? 1 : 0;

branch_processor_state[0] <= processing_branch;

end

processing_branch:

begin

decision[current_tdr_address] <= greater_than_false_address[0] & less_than_true_address[0];

end

All synthesizes well with the same logic and memory usage statistics until I add the single assignment in the processing_branch case.

I checked my settings and the max_number_of_uninferred_ram_logic is set to -1 (no max). Have attempted to read up on inferred/uninferred ram. It seems that the documentation would be quite helpful for someone that already understood the paradigm. However, I am having trouble converting that written academics to the practical problem that I have (I'm not the sharpest tool in the shed).

Any help is greatly appreciated....

ME