Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVerilog Synthesis Q
Am bumping into a synthesis problem inside of an always construct. Simplified code is reg true_or_false[0:9999]; reg a; always (negedge clk) begin if (a <5000) true_or_false...
Altera_ForumHonored Contributor
Honored ContributorBesides observing the conditions for RAM inference, you should think about the data type of reg a. It's a bit variable, how can it address a memory array?
