Verilog Synthesis Q

Your simplified code isn't very clear.

But from the looks of the message, you're designing something that requires a huge number of register (more than the FPGA has) and can't be converted to use SRAM.

What you need to do is to try and re-write your code in such a way that it uses SRAM and meets Quartus HDL SRAM templates.

See the HDL coding guidelines handbook for details.