Verilog Syntax Error

Question

I received this error while following a tutorial in a Verilog book:

Error (10170): Verilog HDL syntax error at resistor.v(3) near text ""disciplines.vams"; expecting ".", or an identifier, or "*", or "/"

Can anyone provide suggestions on how to fix this?

Thanks.

altera_forum · Answer

Are you trying to compile Verilog-AMS in Quartus II or ModelSim?

altera_forum · Answer

Does analog/mixed signal not work in Quartus II? I am using a text that refers to Verilog-AMS.

Also, another error pops up for the other modules I wrote:

Error (10170): Verilog HDL syntax error at capacitance.v(3) near text ""disciplines.vams"; expecting "<"

Thanks for the help.

altera_forum · Answer

--- Quote Start ---  Does analog/mixed signal not work in Quartus II?  --- Quote End ---    No...How would it?  -- slacker

altera_forum · Answer

Quartus II and ModelSim does not support Verilog-AMS.  You need to ADMS compiler like QuestaADMS from Mentor.

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