Verilog process not implemented correctly in Quartus

Thanks for all your replies, I appreciate it.

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What Quartus Version are you using ?

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9.1 sp1 build 304

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if 1 compilation is working and 1 not, what about the others ?

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I have changed the coding to be more compliant with the recomended HDL coding guidelines, and it seems work properly for this compilation (then again it could be just a "lucky" compilation and the next one will fail again, as happened before).

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one thing that i am not shure is, shouldn't you write

always @(posedge clk or negedge rst_n)

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SystemVerilog

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Did you specify the initial values for hdr_frame_length_s ?

like

reg [15:0] hdr_frame_length_s = 16'd1;

or during

initial

begin

hdr_frame_length_s = 16'd1;

end // of initialiser block

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the code is synthesizable, register is initialized @ negedge rst_n

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Do you get any warnings during compilation ?

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Not any that seem related