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Hi,
It seems as though the following synchronous process in Verilog is sometimes not implemented correctly by Quartus. Why?
always @(posedge clk, negedge rst_n)
if (!rst_n)
begin
hdr_frame_length_s[15:0] <= 1;
end
else if (!srst_n || sof)
begin
hdr_frame_length_s[15:0] <= 1;
end
else if (valid_in)
begin
hdr_frame_length_s <= hdr_frame_length_s + 1;
end
The code above worked as intended in at least one compilation. However in at least one other compilation, sof would not reset the register.
There are two non-standard things here, first the register is reset to 1 not 0, and second the synchronous reset is a logical OR of two inputs.
Why is this code problematic to Quartus?
Thanks for you help,
Avshalom.
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Hi,
how the signals !srst_n and sof generated ? Outside the FPGA ?
Kind regards
GPK
Honored Contributor
