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Altera_Forum's avatar
Altera_Forum
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16 years ago

Verilog design and testbench

How to differentiate verilog design and testbench syntax? Is it depending on the some symbol like# , $ and so on? is all the syntax with symbol for testbench? $random is for test bench? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Basically, i just want to know the code written(syntax) is for RTL design or testbench. It is because i download the summary of verilog where it contains syntax for testbench and RTL design.