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Altera_Forum's avatar
Altera_Forum
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12 years ago

verilog case statement

hi , i am facing a problem in verilog case statement .when i put inputs (00,01,10,11) at inputs 00 and 10 to cntrl1 and cntrl2, it outputs the value from in0. i use Xilinx software and my code i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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did you mean case ({cntrl1,cntrl2}) instead of case ({cntrl2,cntrl2})

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u r right .

thnkx