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Altera_Forum
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14 years ago

Verilog "case" collision problem

case( 1'b1 ) // synthesis parallel_case a:value <= 4'd1; b:value <= 4'd2; c:value <= 4'd3; d:value <= 4'd4; endcase if there is only 1 condition equals,the synthesis result is parall...
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Altera_Forum
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14 years ago

If you mean your case subject is 8 bits then you can say:

case subject

"00000000": do this

"00000001": do that

...etc

you may use better syntax than me as my Verilog is rusty.