Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Verilog "case" collision problem

case( 1'b1 ) // synthesis parallel_case a:value <= 4'd1; b:value <= 4'd2; c:value <= 4'd3; d:value <= 4'd4; endcase if there is only 1 condition equals,the synthesis result is parall...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

actually,in my design,there are 8 case variables ,so if I use the priority structure like "if(a==1)..else if(b==1)...else if(c==1)...",the path delay will be very long!

So I want to use the parallel structure as above described.

"looks like your case statement is upside down"----I have tested the codes,it will be synthesised as parallel circuit because of the "synthesis parallel_case" .