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Altera_Forum
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14 years ago

Verilog "case" collision problem

case( 1'b1 ) // synthesis parallel_case a:value <= 4'd1; b:value <= 4'd2; c:value <= 4'd3; d:value <= 4'd4; endcase if there is only 1 condition equals,the synthesis result is parall...
Altera_Forum's avatar
Altera_Forum
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14 years ago

your case statement must cater for all cases including default.

So your question is not right. Your case variable cannot have two values at same time.

Edit: looks like your case statement is upside down