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Altera_Forum
Honored Contributor
Honored Contributorverilog and vhdl in one project
I used vhdl in my fpga project before,but I want to use veriog now. Is there any conflict problem when I use vhdl and veriog in the same project,because I need the modual which I had finished before.and I write my new programe in verilog.thank you!
2 Replies
Altera_ForumThe only problem will be Modelsim. You won't be able to simulate a mixed project with the basic edition of Modelsim-Altera.
- Altera_Forum
There is no problem in mixing code.
You only need to export the instantiation code of the module in order to import it in the different language.
