Verilog-2001 Variable Declaration With Initialization Synthesis

I wanted to initialize some registers on power up to a default state. I noticed verilog 2001 permits variable declaration with initialization. Like this:

reg foo = 1'b1;

This is similar to an initial statement. My observation is that Quartus does in fact synthesize this to drive a default value on power up. However, my understanding was the initial statement was used for test benches, but ignored during synthesis. Is this just a fluke, or can I rely on this to work correctly in HW.

Thanks.