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Altera_Forum
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7 years ago

Verifying Configuration Memory after Programming

I'm working on an application for a high EMI environment and need to constantly verify the configuration of an FPGA to ensure that the circuit isn't being damaged/altered by the noise. I know I can ...
Altera_Forum's avatar
Altera_Forum
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7 years ago

That looks like it could work. I'm also investigating CPLDs for this use case, is there anything similar for those? I see that the MAX10 family can use the SEU IP but I don't see anything about the MAX V family. Ideally I'd like to be able to do a real-time checksum on the program memory and verify that it's still good.