VCO post-scale problem

I’m using the alt pll reconfig IP to generate different output frequency and confonting a problem which puzzles me long.

The output frequency of PLL can be calculated as follows:

Fout=F_in× (M/(N×C))

In which:

F_in is the input frequency;

M is the Feedback counter (M);

N is the Pre-scale counter (N);

C is Post-scale output counters (C0–C4）

The inner diagram of pll:

1.jpg

The blue circles check out the M,N,C, please notes the red circle which checks out the VCO post-scale counter K. And I’ve got some doubts about this VCO post-scale counter K.

Let 50Mhz clock as input clock and 126Mhz as output clock. Now the parameters is like below:

2.jpg

We can know from the picture that

M=63,N=5,C=5

And the output frequency is:50*63/(5*5)=126Mhz

Please note the red circle which checks out the VCO post scale counter is 2.

In some other case the I set the output frequency is 138Mhz, and now the parameter is:

3.jpg

M=69,N=5,C=5

The output frequency is:50*69/（5*5）=138Mhz

But pls look at the picture:

In which the VCO post scale counter is 1

I just want to ignore this VCO post scale counter, but in pll reconfig IP this para is used:

4.jpg

So,would anybody could tell me how to calculate this VCO post scale parameter?