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Altera_Forum
Honored Contributor
Honored ContributorVarible clock rate
Hello together I have a verilog-module that is working with an external 25 MHz clock. Now in my application I would like to work with a variable clock rate. Some other logic modules in the FPG...
Altera_ForumHonored Contributor
Honored ContributorHi Geri,
I'm glad that I found your code. But when I cut & pasted and attempted to simulate it with Fclk = 24 MHz, the clockout didn't come out as expected. First, the ModelSim gave a warning that the number 3422275754 will be a signed integer and will cause overflow. Second, without any hard reset at the beginning to set the accumulator to a default value (all 0's in this case), the subsequent accumulations resulted in all red in ModelSim. 3rd, the clock enable pulse is not a single pulse when FOut (~19 MHz) is so close to the sampling clock, Fclk, at 24 MHz. I've noticed when the sampling clock, Fclk, is at least 10 times the generated clock, FOut, then it would work! Can you/anyone provide some inputs into how to generate a variable clock with fine resolution. Thank you.
