Varible clock rate

Hello kaz

// Verilog module for variable clock generation triggering logic
// fOut = fclk * ClockGeneratorAccInc/2^32  
// Accumulator increment value = fout/fOsc * 2^32; 
// e.g.  value = 19123456/24000000 * 2^32 = 3422275754
module DDS(clk, ClkEnable); 
input clk; 
output ClkEnable;  
 
parameter ClockGeneratorAccWidth = 32;  // plus overflow bit reg
ClockGeneratorAccWidth:0] ClockGeneratorAcc;  always @(posedge clk) 
 
begin     
    ClockGeneratorAcc <= ClockGeneratorAcc + 3422275754; // 19123456 MHz
end
 
// Use the highest bit of the counter (MSB) to enable clock
assign ClkEnable = ClockGeneratorAcc;
endmodule
 
// Example of use
// because ClkOut is toggeling we have the half frequency on output pin:)
module TestDDS(clk, fOut);
input clk;
output fOut;
wire cEn;
reg ClkOut;
DDS ClockGenerator(.clk(clk),.ClkEnable(cEn));
always @(posedge clk)
begin
 if (cEn) ClkOut = ~ClkOut;
end
assign PWM = ClkOut;
endmodule