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Altera_Forum
Honored Contributor
Honored ContributorVarible clock rate
Hello together I have a verilog-module that is working with an external 25 MHz clock. Now in my application I would like to work with a variable clock rate. Some other logic modules in the FPG...
Altera_ForumHonored Contributor
Honored ContributorThanks to all of you for the fast response and the approaches!
@Kaz: Thats sounds very fine and simple and no DDS is necessary. Attached my understanding. Does this piece of code reflect your approach?
// Verilog module for clock variable clock generation of logic
module DDS(clk, ClkEnable);
input clk;
output ClkEnable;
// Binary counter, 16-bits wide
parameter ClockGeneratorAccWidth = 33; // plus overflow bit
parameter ClockGeneratorAccIncWidth = 32;
reg ClockGeneratorAcc;
reg ClockGeneratorAccInc = 2345; // any value for frequency setting e.g. 2345
always @(posedge clk)
begin
ClockGeneratorAcc <= ClockGeneratorAcc + ClockGeneratorAccInc;
if (ClockGeneratorAcc == 1) ClockGeneratorAcc <= 0;
end
// Use the highest bit of the counter (MSB) to enable clock
assign ClkEnable = ClockGeneratorAcc;
endmodule
