Varible clock rate

Thanks to all of you for the fast response and the approaches!

@Kaz: Thats sounds very fine and simple and no DDS is necessary.

Attached my understanding. Does this piece of code reflect your approach?

// Verilog module for clock variable clock generation of logic
module DDS(clk, ClkEnable);
input clk;
output ClkEnable;
// Binary counter, 16-bits wide
parameter ClockGeneratorAccWidth = 33;  // plus overflow bit
parameter ClockGeneratorAccIncWidth = 32;
reg  ClockGeneratorAcc;
reg  ClockGeneratorAccInc = 2345; // any value for frequency setting e.g. 2345
always @(posedge clk) 
begin
    ClockGeneratorAcc <= ClockGeneratorAcc + ClockGeneratorAccInc;
    if (ClockGeneratorAcc == 1) ClockGeneratorAcc <= 0;
end
// Use the highest bit of the counter (MSB) to enable clock
assign ClkEnable = ClockGeneratorAcc;
endmodule

@FvM

The AD9834 has an integrated comparator that can be conected to the sin wave output to create a rectangular signal. So if I understand you right, the approach with the external DDS could work but what percentage do

you estimate has it lower than the DDS frequency?

Friendly regards and thank you again

Geri