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Altera_Forum
Honored Contributor
Honored ContributorVarible clock rate
Hello together I have a verilog-module that is working with an external 25 MHz clock. Now in my application I would like to work with a variable clock rate. Some other logic modules in the FPG...
Altera_ForumHonored Contributor
Honored ContributorThere are two possible variants of using DDS techniques for digital clock generation:
- The basic variant is to use only the fractional frequency divider of the DDS designs. You get an effectively unlimited frequency resolution, but the output clock has a jitter. - The extended variant uses the low pass filtered sine output of the DDS and a comparator to generate an interpolated digital clock. To be able to reduce output jitter in the low pass filter, the maximum generated frequency must be considerably lower than the DDS clock. In practise, a DDS design is the only simple way to generate a stepwise variable frequency. Alternatively a PLL with a reference frequency of 1 Hz can do, but it would be rather slow. Or a PLL with e.g. 32 or 64 Hz reference frequency and a post divider.
