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Altera_Forum
Honored Contributor
Honored ContributorVarible clock rate
Hello together I have a verilog-module that is working with an external 25 MHz clock. Now in my application I would like to work with a variable clock rate. Some other logic modules in the FPG...
Altera_ForumHonored Contributor
Honored ContributorThe DDS chip is well known solution for clk generation. But it is only justified if you want a clean clk every time. Alternatively you can design a dds-like module in your rtl. This can generate any rate which can be applied as clk enable for a fixed 25MHz.
The idea is very simple: just a free running 2^n accummulator with variable increment. use its overflow pulse signal as enable. for example if your accum. is 32 bits wide then run it on 25MHz. if the increment value is say 2345 then the enable rate = 2345/2^32 of clk rate. i.e. freq = 25000000 * incr/2^32 in Hz. This is the very idea used by commercial DDS... make sure that the pulse is one clk short. the easiest way for this is to use 33 bits for 32 bit accum. to let it overflow without loss of count.
