variable reset simple question

I already tried that but gives some error and I thought is invalid

"cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct"...

can you explain a little bit ? In addition, I need cnt to be blocking if possible

well, I solved a bit but isn't full working

always @(posedge clkin or posedge OE)

if(OE)

cnt = 0;

else

begin

.... other actions on posedge clkin possible only here but I need them always

end

cnt = cnt + 1;

and when OE=1 no more counter increment. Can you suggest something please? I am trouble understanding what's behind yet since I'm used to circular flow like C. Thanks very much.

It's not possible to increment the counter and at the same time reset it.

You need to choose your priorities.

clk has priority and OE is read synchronously with one cycle delay:

always @(posedge clkin) begin
     reg OE_D;
     OE_D <= OE;
     if (OE && ~OE_D) begin // synchronously detect rising edge of OE 
          cnt <= 0;
     end else begin
          cnt <= cnt + 1;
     end
end

Otherwise you will need the other version, more economical (only a single register), but does not count up while OE =1

always @(posedge clkin or posedge OE) begin
  if(OE) begin
    cnt <= 0;
  end else begin
    cnt <= cnt + 1;
  end
end

Which tool gives you the error:

"cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct"...

And how exactly did the code that triggered that error looked like ?

Dear Sir,

This is exactly what I need, thank you very much!

Memorize old_value and upon next clock goes HI, will have the situation old=LO and new=HI. Detecting only rising edge.

Have a good day both,

PS. Nevermind, error was given by using

always @(posedge clock and posedge OE)

if (!OE) would be error

I have to get familiar with verilog :)

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I have to get familiar with verilog

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Yes. Did you notice the language templates accessible in the Quartus editor context menu. They are providing example code for similar basic constructs.

Hi,

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Dear Sir,

I need cnt to be blocking if possible

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It would be a very bad style trying model Sequential logic using blocking assigns. Use NBA instead.

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I have to get familiar with verilog :)

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Yes, pick up a good book like Palnitkar/Bhasker to start with. If your company has it, use a LINT tool (such as ALINT from www.aldec.com).

Good Luck

Srini

www.cvcblr.com/blog

Thank you all, I solved, great community.

Btw. I changed all possible vars to NBA and saved few extra macrocells :) Simulation looks great and I'm very confident since no warnings except main clock undefined or so, no timing problems. This was just a minor update of a working project designed few moths ago. And however, I want to congratulate Quartus team, compared at least to Xilinx and worse Lattice it's a great job!

We face now a terrible problem. Our prototype which includes this EPM3064 will be homologate somewhere in september but we cannot find anywhere to buy industrial version EPM3064ATI. As far as I heard from my colleagues, will be tested at -33deg C. There is no speed constraints since CPLD works at most on several hundred KHz but at all distributors there is only commercial version and industrial has 26 weeks delivery time.

Does anyone knows Altera can send some samples? Can I fill some urgent request somewhere? Or to buy from somewhere else (we try Farnell, Digikey, Avnet, Future).

Best regards,

PS. We have old projects already with C versions working. Anyone knows if we know clock is under 1MHz can we use at -33deg ? (even my boss will now allow)

Talk to your local FAE and/or Sales rep with regards to part procurement. They're really the only ones who can help you there.

Jake